Without CAD tools, large chips can not be designed in time or within budget. Underlying circuit technologies, however, are constantly changing. If CAD tools are technology dependent, then they need constant modification with every change in technology. This is an expensive proposition.
Usually, the technology dependent components of a CAD system are kept separate so that the tools do not require constant tinkering. Each CAD tool usually recognizes a common, small set of primitives. All technology specific elements are then described by using these primitives for the use by these tools.
The process of expressing behavior of a technology specific entity by primitives recognized by a target CAD tool is called "library" or "rules" or "model" creation. Creation of libraries usually is a two way street, consisting of mapping a technology specific entity to a set of primitives and then verifying that the library/model/rule thus created is a correct representation. The verification of all the rules, however, is extremely time consuming.
In known ASIC designs, designers are free only to make choices among only a given, narrow set of library elements. This may inhibit a designer from reaching his/her design goals. A more open set of technology specific entities, however, calls for larger libraries or the creation of a library on demand which the designer may not be trained to do. An ideal solution, therefore, would be to create further software tools that can generate these libraries automatically, providing flexibility and uniformity.
The present invention is one such tool. The method of the invention can accept a transistor level netlist and produce a gate level description for automatic test pattern generation purposes. The software environment of the invention is flexible enough to tailor to various user needs.